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Ordering number : ENA1384A
LC87F2J32A
Overview
CMOS IC FROM 32K byte, RAM 1024 byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC87F2J32A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (On-boardprogrammable), 1024-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 12/8-bit 14-channel AD converter, a system clock frequency divider, remote control receive, an internal reset and a 24-source 10-vector interrupt feature.
Features
Flash ROM * Capable of on-board-programming with wide range (2.2 to 5.5V) of voltage source. * Block-erasable in 128-byte units * Writable in 2-byte units * 32768 x 8 bits RAM * 1024 x 9 bits Minimum Bus Cycle * 83.3ns (12MHz) VDD=2.7 to 5.5V * 100ns (10MHz) VDD=2.2 to 5.5V * 250ns (4MHz) VDD=1.8 to 5.5V Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.20
42209HKIM 20090406-S00001 No.A1384-1/30
LC87F2J32A
Minimum Instruction Cycle Time * 250ns (12MHz) VDD=2.7 to 5.5V * 300ns (10MHz) VDD=2.2 to 5.5V * 750ns (4MHz) VDD=1.8 to 5.5V Ports * Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units * Dedicated oscillator ports/input ports * Reset pin * Power pins
39 (P0n, P1n, P2n, P30 to P36, P70 to P73, PWM0, PWM1, XT2, CF2) 2 (CF1, XT1) 1 (RES) 6 (VSS1 to 3, VDD1 to 3)
Timers * Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) * Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz) 2) Can generate output real-time SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2-bit in continuous data transmission) * Built-in baudrate generator
No.A1384-2/30
LC87F2J32A
AD Converter: 12 bits/8 bits x 14 channels * 12/8 bits AD converter resolution selectable PWM: Multifrequency 12-bit PWM x 2 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) 1) Noise rejection function (Units of noise rejection filter : about 120s, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of halt-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X'tal HOLD mode release function Clock Output Function * Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. * Can generate the source clock for the subclock. Watchdog timer * External RC watchdog timer * Interrupt and reset signals selectable Interrupts * 24 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/REMOREC2 INT3/INT5/ BT0/BT1 T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/T6/T7 Port 0/T4/T5/PWM0, PWM1 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. * IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table above). Subroutine Stack Levels: 512 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time)
No.A1384-3/30
LC87F2J32A
Oscillation Circuits * Internal oscillation circuits 1) Low-speed RC oscillation circuit : For system clock(100kHz) 2) Medium-speed RC oscillation circuit : For system clock(1MHz) 3) Frequency variable RC oscillation circuit: For system clock(8MHz) (1) Adjustable in 0.5% (typ) step from a selected center frequency. (2) Measures oscillation clock using a input signal from XT1 as a reference. * External oscillation circuits 1) Low speed crystal oscillation circuit: For low-speed system clock, with internal Rf 2) Hi-speed CF oscillation circuit: For system clock, with internal Rf (1) Both the CF and crystal oscillator circuits stop operation on a system reset. System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). Internal Reset Function * Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. * Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Occurrence of an interrupt * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an interrupt source established in the infrared remote controller receiver circuit
No.A1384-4/30
LC87F2J32A
On-chip Debugger * Supports software debugging with the IC mounted on the target board (LC87D2J32A). LC87F2J32A has an On-chip debugger but its function is limited. Data Security Function (flash versions only) * Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. Package Form * SQFP48 (7x7): * QIP48E (14x14): * FLGA49 (5x5):
Lead-/Halogen-free type Lead-free type Lead-free type (This package is Built To Order.)
Development Tools * On-chip debugger: TCB87- TypeB + LC87D2J32A Programming Board
Package SQFP48 (7x7) QIP48E (14x14) Programming boards W87F55256SQ W87F55256Q
Flash ROM Programmer
Maker Single programmer Flash Support Group, Inc. (FSG) Gang programmer Model AF9708 AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) AF9723/AF9723B(Main body) (Including Ando Electric Co., Ltd. models) AF9833(Unit) (Including Ando Electric Co., Ltd. models) Flash Support Group, Inc. (FSG) + Sanyo (Note 1) Single/Gang programmer SANYO In-circuit/ Gang programmer In-circuit programmer SIB87(Inter Face Driver) (SANYO model) SKK/SKK Type B (SANYO FWS) SKK-DBG Type B (SANYO FWS) Application Version 1.04 or later Chip Data Version 2.16 or later LC87F2J32A AF9101/AF9103(Main body) (FSG models) (Note 2) LC87F2J32A Rev 03.07 or later LC87F2J32A Supported version Device
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from SANYO (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or SANYO for the information.
No.A1384-5/30
LC87F2J32A
Package Dimensions
unit : mm (typ) 3163B
9.0 7.0 36 37 25 24
48 1 0.5 (0.75) 12 0.18
13
7.0 9.0
0.15
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
Package Dimensions
unit : mm (typ) 3156A
17.2 0.8 24 14.0 13 1 1.0 (1.5) (2.7) 0.35 12 0.15 17.2 14.0 36 37 25
48
3.0max
0.1
SANYO : QIP48E(14X14)
0.5
No.A1384-6/30
LC87F2J32A
Pin Assignment
P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P07/T7O/AN7 P06/T6O/AN6 P05/CKO/AN5 P04/AN4 36 35 34 33 32 31 30 29 28 27 26 25
P36 P35 VDD3 VSS3 P34 P33 P32/DBGP2 P31/DBGP1 P30/DBGP0 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
37 38 39 40 41 42 43 44 45 46 47 48
LC87F2J32A
24 23 22 21 20 19 18 17 16 15 14 13
P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1
P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1/AN12 CF2/AN13 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1
1 2 3 4 5 6 7 8 9 10 11 12
Top view
SANYO: SQFP48 (7x7) SANYO: QIP48E (14x14)
SQFP/QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1/AN12 CF2/AN13 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ SQFP/QIP 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM1 PWM0 VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/CKO/AN5 P06/T6O/AN6 P07/T7O/AN7 P20/UTX/INT4/T1IN P21/URX/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN NAME
"Lead- / Halogen-free Type" "Lead-free Type"
NAME P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN P36 P35 VDD3 VSS3 P34 P33 P32/DBGP2 P31/DBGP1 P30/DBGP0 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
SQFP/QIP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
No.A1384-7/30
LC87F2J32A
System Block Diagram
Interrupt control
IR
PLA
Standby control
Flash ROM
CF/ X'tal SRC RC MRC RES Reset control Clock generator
PC
WDT Reset circuit (LVD/POR)
ACC
B register
SIO0
Bus interface
C register
SIO1
Port 0 ALU
Timer 0
Port 1
Timer 1
Port 2
PSW
Timer 4
Port 3
RAR
Timer 5
Port 7
RAM
Timer 6
ADC
Stack pointer
Timer 7
UART1
Watchdog timer
Base timer
Remote control receiver circuit INT0-2, INT4, 5 INT3 (Noise filter)
On-chip debugger
PWM0
PWM1
No.A1384-8/30
LC87F2J32A
Pin Description
Pin Name VSS1 to VSS3 VDD1 to VDD3 Port 0 P00 to P07 I/O I/O - power supply pins + power supply pin * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * HOLD reset input * Port 0 interrupt input * Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P07(AN7): AD converter input Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input Interrupt acknowledge type Rising INT4 INT5 enable enable Falling enable enable Rising & Falling enable enable H level disable disable L level disable disable Yes Yes Description Option No No Yes
Port 3 P30 to P36
I/O
* 7-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins On-chip debugger pins: DBGP0 to DBGP2 (P30 to P32)
Yes
Continued on next page.
No.A1384-9/30
LC87F2J32A
Continued from preceding page.
Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input P70(AN8), P71(AN9) : AD converter input Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No
PWM0, PWM1 RES XT1
I/O I/O Input
* PWM0 and PWM1 output ports * General-purpose I/O available External reset Input/internal reset output * 32.768kHz crystal oscillator input pin * Shared pins General-purpose input port AD converter input port: AN10
No No No
XT2
I/O
* 32.768kHz crystal oscillator output pin * Shared pins General-purpose I/O port AD converter input port: AN11
No
CF1
Input
Ceramic resonator input pin * Shared pins General-purpose input port AD converter input port: AN12
No
CF2
Output
Ceramic resonator output pin * Shared pins General-purpose I/O port AD converter input port: AN13
No
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip Debugger Installation Manual" Recommended Unused Pin Connections
Port Name P00 to P07 P10 to P17 P20 to P21 P30 to P36 P70 to P73 PWM0,PWM1 XT1 XT2 CF1 CF2 Open Open Open Open Open Open Pulled low with a 100k resistor or less Open Pulled low with a 100k resistor or less Open Recommended Unused Pin Connections Board Output low Output low Output low Output low Output low Output low General-purpose input port Output low General-purpose input port Output low Software
No.A1384-10/30
LC87F2J32A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 1 bit 1 2 P20 to P27 1 bit 1 2 P30 to P36 1 bit 1 2 P70 P71 to P73 PWM0, PWM1 XT1 XT2 No No No No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS CMOS Input for 32.768kHz crystal oscillator (Input only) Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) CF1 CF2 No No Input for ceramic resonator oscillator (Input only) Output for ceramic resonator oscillator (Nch-open drain when in general-purpose output mode) No No No Output Type Pull-up Resistor Programmable (Note 1) Programmable (Note 1) Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No No
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low- and high-impedance pull-up connection is exercised in 1-bit units.
No.A1384-11/30
LC87F2J32A
User Option Table
Option name Port output type P00 to P07 1 bit Option to be applied on Flash-ROM version Option selected in units of CMOS Nch-open drain CMOS P10 to P17 1 bit Nch-open drain CMOS P20 to P27 1 bit Nch-open drain CMOS P30 to P36 Program start address Low-voltage detection reset function Power-on reset function Detect function Detect level Power-On reset level 1 bit Nch-open drain 00000h 07E00h Enable: Use Disable: Not Used 7-level 8-level Option selection
Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1: During backup in hold mode, port output `H' level is supplied from the back-up capacitor.
LSI Back-up capacitor Power Supply VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2: During backup in hold mode, output is not held high and its value in unsettled.
LSI Back-up capacitor Power Supply VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A1384-12/30
LC87F2J32A
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) Mean output High level output current current (Note 1-1) IOMH(2) IOMH(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) Peak output current IOPL(2) IOPL(3) Mean output Low level output current current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) Power dissipation Pd max(1) Pd max(2) IOML(1) IOPL(1) PWM0, PWM1 P71 to P73 P71 to P73 Port 0 Port 1, PWM0, PWM1 Ports 0, 1, PWM0, PWM1 Ports 2, P35, P36 P30 to P34 Pots 2, 3 P02 to P07, Ports 1, 2, 3, PWM0, PWM1 P00, P01 Port 7, XT2, CF2 P02 to P07, Ports 1, 2, 3, PWM0, PWM1 P00, P01 Port 7, XT2, CF2 Port 7, XT2, CF2 Port 0 Port 1, PWM0, PWM1 Port 0, 1, PWM0, PWM1 Ports 2, P35, P36 P30 to P34 Ports 2, 3 SQFP48 (7x7) Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta=-40 to +85C Package only Ta=-40 to +85C Package with thermal resistance board (Note 1-2) Pd max(3) Pd max(4) QIP48E (14x14) Ta=-40 to +85C Package only Ta=-40 to +85C Package with thermal resistance board (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 +85 C +125 489 281 356 mW Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins 20 7.5 15 45 45 80 45 45 60 139 Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin 15 30 10 Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin 20 Total of all applicable pins Per 1 applicable pin Total of all applicable pins Total of all applicable pins Total of all applicable pins IOMH(1) PWM0, PWM1 P71 to P73 Ports 0, 1, 2, 3 Per 1 applicable pin CMOS output select Per 1 applicable pin IOPH(1) VI VIO XT1, CF1 Ports 0, 1, 2, 3, Port 7, PWM0, PWM1, XT2, CF2 Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -10 -20 -5 -7.5 -15 -3 -10 -25 -25 -45 -25 -25 -45 mA -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit
Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1x114.3x1.6tmm, glass epoxy) is used.
No.A1384-13/30
LC87F2J32A
Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2, 3, P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) VIH(4) Low level input voltage VIL(1) Port 0 Port 70 watchdog timer side XT1, XT2, CF1, CF2, RES Ports 1, 2, 3, P71 to P73 P70 port input/ interrupt side PWM0, PWM1 VIL(2) Port 0 4.0 to 5.5 1.8 to 4.0 VIL(3) VIL(4) Instruction cycle time (Note 2-1) External system clock frequency FEXCF CF1 * CF2 pin open * System clock frequency division ratio=1/1 * External system clock duty= 505% * CF2 pin open * System clock frequency division ratio=1/2 * External system clock duty= 505% Oscillation frequency range (Note 2-3) FmCF(3) CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 10MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. See Fig. 1. CFLAMP=0) 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) See Fig. 1. 2.2 to 5.5 4 1.8 to 5.5 4 MHz 2.7 to 5.5 2.2 to 5.5 12 10 2.0 to 5.5 0.2 8 3.0 to 5.5 0.2 24.4 1.8 to 5.5 0.1 4 MHz tCYC (Note 2-2) Port 70 watchdog timer side XT1, XT2, CF1, CF2, RES 1.8 to 5.5 1.8 to 5.5 2.7 to 5.5 2.2 to 5.5 1.8 to 5.5 2.7 to 5.5 VSS VSS VSS VSS 0.245 0.294 0.735 0.1 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 200 12 s 1.8 to 4.0 VSS 0.2VDD 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 4.0 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VSS VDD VDD VDD 0.1VDD +0.4 V 1.8 to 5.5 0.3VDD +0.7 VDD Symbol VDD(1) VDD(2) VDD(3) VHD VDD1=VDD2=VDD3 Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.245stCYC200s 0.294stCYC200s 0.735stCYC200s RAM and register contents sustained in HOLD mode. 1.6 5.5 min 2.7 2.2 1.8 Specification typ max 5.5 5.5 5.5 unit
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2.
Continued on next page.
No.A1384-14/30
LC87F2J32A
Continued from preceding page.
Parameter Oscillation frequency range (Note 2-3) FmMRC(2) Symbol FmMRC(1) Pin/Remarks Conditions VDD[V] Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) (Note 2-4) MHz Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) Ta=-10 to +50C FmRC FmSRC FsX'tal Frequency variable RC oscillation usable range Frequency variable RC oscillation adjustment range VmADJ(2) VmADJ(3) Each step of VMFCHBn Each step of VMDCHn 2.4 to 5.5 2.4 to 5.5 0.7 0.2 1.5 0.5 2.3 1.1 % VmADJ(1) Each step of VMRCHBn 2.4 to 5.5 3.6 7.0 11 OpVMRC XT1, XT2 oscillation Internal Low-speed RC oscillation 32.768kHz crystal oscillation See Fig. 3. Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) 2.4 to 5.5 6 8 10 MHz (Note 2-4) 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 0.5 50 1.0 100 32.768 2.0 200 kHz Internal Medium-speed RC 2.4 to 5.5 7.6 8.0 8.4 2.4 to 5.5 7.44 8.0 8.56 min Specification typ max unit
Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100s or longer after the multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1384-15/30
LC87F2J32A
Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, 3 Ports 7 RES PWM0, PWM1 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2, CF2 CF1 Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Ports 0, 1, 2, 3 Port 7 Port 0 Port 7, XT2, CF2 P00, P01 PWM0, PWM1, P05(System clock output function used) IOH=-0.8mA IOL=10mA IOL=1.4mA IOL=0.8mA IOL=25mA IOL=4mA IOL=2mA IOL=1.4mA IOL=0.8mA VOH=0.9VDD When Port 0 selected low-impedance pull-up. VOH=0.9VDD When Port 0 selected High-impedance pull-up. Hysteresis voltage VHYS(2) VHYS(1) Ports 1, 2, 3, 7, RES, XT2 2.7 to 5.5 0.1 VDD 0.07 VDD 10 pF V XT1, XT2, CF2 CF1 Ports 0, 1, 2, 3, P71 to P73 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) Input port selected VIN=VDD VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) Input port selected VIN=VSS VIN=VSS IOH=-1mA IOH=-0.35mA IOH=-0.15mA IOH=-6mA IOH=-1.4mA 1.8 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 1.8 to 4.5 15 18 35 50 -1 -15 VDD-1 VDD -0.4 VDD -0.4 VDD-1 VDD -0.4 VDD -0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 80 230 k 1.8 to 5.5 100 210 400 V 1.8 to 5.5 -1 1.8 to 5.5 1.8 to 5.5 1 15 A 1.8 to 5.5 1 min Specification typ max unit
Ports 0, 1, 2, 3, PWM0, PWM1,
1.8 to 2.7 All pins For pins other than that under test: VIN=VSS, f=1MHz, Ta=25C
Pin capacitance
CP
1.8 to 5.5
No.A1384-16/30
LC87F2J32A
Serial Input/Output Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time Data hold time tsDI(1) thDI(1) SB0(P11), SI0(P11) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. Output delay Input clock time tdD0(2) tdD0(3) Output clock tdD0(1) SO0(P10), SB0(P11) * Continuous data transmission/reception mode (Note 4-1-2) * Synchronous 8-bit mode (Note 4-1-2) (Note 4-1-2) 1.8 to 5.5 1.8 to 5.5 0.05 0.05 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6 1.8 to 5.5 1/2 tSCK 1/2 4/3 tSCKH(1) Symbol tSCK(1) tSCKL(1) 1.8 to 5.5 Pin/Remarks SCK0(P12) Conditions VDD[V] * See Fig. 6. min 2 1 1 tCYC Specification typ max unit
Serial clock
(1/3)tCYC +0.08 1tCYC +0.08 s
Serial output
(1/3)tCYC +0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. 2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time Data hold time tsDI(2) thDI(2) SB1(P14), SI1(P14) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 1.8 to 5.5 (1/3)tCYC +0.08 s 1.8 to 5.5 0.05 0.05 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 1.8 to 5.5 1/2 tSCK 1/2 tSCKH(3) Symbol tSCK(3) tSCKL(3) 1.8 to 5.5 Pin/Remarks SCK1(P15) Conditions VDD[V] * See Fig. 6. min 2 1 tCYC 1 2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Serial clock
No.A1384-17/30
LC87F2J32A
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23) INT5(P24 to P27) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES * Resetting is enabled. 1.8 to 5.5 200 s * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 1.8 to 5.5 256 * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 1.8 to 5.5 64 * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. 1.8 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 1.8 to 5.5 1 min Specification typ max unit
AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V <12bits AD Converter Mode at Ta = -40 to +85C>
Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) AN12(CF1) AN13(CF2) Analog input voltage range Analog port input current IAINH(1) IAINL(1) IAINH(2) IAINL(2) analog channel except AN12 AN12 VAIN=VDD VAIN=VSS VAIN=VDD VAIN=VSS VAIN * See Conversion time calculation formulas. (Note 6-2) * See Conversion time calculation formulas. (Note 6-2) (Note 6-1) (Note 6-1) Conditions VDD[V] 2.4 to 5.5 3.0 to 5.5 2.4 to 3.6 4.0 to 5.5 3.0 to 5.5 2.4 to 3.6 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 -15 -1 15 32 64 410 VSS min Specification typ 12 16 20 115 115 425 VDD 1 A V s max unit bit LSB
Note 6-1: The quantization error (1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: * The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. * The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
No.A1384-18/30
LC87F2J32A
<8bits AD Converter Mode at Ta = -40 to +85C>
Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) AN12(CF1) AN13(CF2) Analog input voltage range Analog port input current IAINH(1) IAINL(1) IAINH(2) IAINL(2) analog channel except AN12 AN12 VAIN=VDD VAIN=VSS VAIN=VDD VAIN=VSS VAIN * See Conversion time calculation formulas. (Note 6-2) * See Conversion time calculation formulas. (Note 6-2) (Note 6-1) Conditions VDD[V] 2.4 to 5.5 2.4 to 5.5 4.0 to 5.5 3.0 to 5.5 2.4 to 3.6 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 -15 -1 15 20 40 250 VSS min Specification typ 8 1.5 90 90 265 VDD 1 A V s max unit bit LSB
Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)x(1/3)xtCYC 8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio))+2)x(1/3)xtCYC
External oscillation (FmCF) CF-12MHz Operating supply voltage range (VDD) 4.0V to 5.5V 3.0V to 5.5V CF-10MHz 4.0V to 5.5V 3.0V to 5.5V CF-4MHz 3.0V to 5.5V 2.4V to 3.6V System division ratio (SYSDIV) 1/1 1/1 1/1 1/1 1/1 1/1 Cycle time (tCYC) 250ns 250ns 300ns 300ns 750ns 750ns AD division ratio (ADDIV) 1/8 1/16 1/8 1/16 1/8 1/32 12bit AD 34.8s 69.5s 41.8s 83.4s 104.5s 416.5s AD conversion time (TCAD) 8bit AD 21.5s 42.8s 25.8s 51.4s 64.5s 256.5s
Note 6-1: The quantization error (1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: * The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. * The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
Power-on reset (POR) Characteristics at Ta = -40 to +85C, VSS1 = VSS2 = VSS3 = 0V
Specification Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions * Select from option. (Note 7-1) Option selected voltage 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS POUKS * See Fig. 8. (Note 7-2) * Power supply rise time from 0V to 1.6V. min 1.55 1.85 1.95 2.25 2.45 2.75 3.73 4.21 typ 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 0.7 max 1.79 2.09 2.19 2.49 2.69 2.99 3.99 4.49 0.95 100 ms V unit
Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation.
No.A1384-19/30
LC87F2J32A
Low voltage detection reset (LVD) Characteristics at Ta = -40 to +85C, VSS1=VSS2=VSS3=0V
Specification Parameter LVD reset Voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions * Select from option. (Note 8-1) (Note 8-3) * See Fig. 9. Option selected voltage 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V LVD hysteresis width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity) TLVDW LVUKS * See Fig. 9. (Note 8-4) * LVDET-0.5V * See Fig. 10. 0.2 ms min 1.81 1.91 2.21 2.41 2.71 3.69 4.18 typ 1.91 2.01 2.31 2.51 2.81 3.79 4.28 55 55 55 55 60 65 65 0.7 0.95 V mV max 2.01 2.11 2.41 2.61 2.91 3.89 4.38 V unit
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation.
No.A1384-20/30
LC87F2J32A
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=12MHz ceramic oscillation mode * System clock set to 12MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * CF1=24MHz external clock * System clock set to CF1 side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDOP(3) * FmCF=10MHz ceramic oscillation mode * System clock set to 10MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(4) * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(5) * CF oscillation low amplifier size selected. (CFLAMP=1) * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/4 frequency division ratio IDDOP(6) * FsX'tal=32.768kHz Crystal oscillation mode * Internal Low speed RC oscillation stopped. * System clock set to internal Medium speed RC oscillation. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDOP(7) * FsX'tal=32.768kHz crystal oscillation mode * Internal Low speed and Medium speed RC oscillation stopped. * System clock set to 8MHz with Frequency variable RC oscillation * 1/1 frequency division ratio IDDOP(8) * External FsX'tal and FmCF oscillation stopped. * System clock set to internal Low speed RC oscillation. * Internal Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(9) * External FsX'tal and FmCF oscillation stopped. * System clock set to internal Low speed RC oscillation. * Internal Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * Ta=-10 to +50C 2.5 35 65 3.3 47 86 5.0 70 145 A 1.8 to 3.6 47 106 1.8 to 5.5 70 173 2.7 to 3.6 3.8 6.6 2.7 to 5.5 5.6 10.8 1.8 to 3.6 0.3 0.8 1.8 to 5.5 0.5 1.5 2.2 to 3.6 0.5 1.1 2.2 to 5.5 0.9 2.2 1.8 to 3.6 1.9 3.9 mA 1.8 to 5.5 2.6 6.1 2.2 to 3.6 3.6 6.7 2.2 to 5.5 5.9 10.5 3.0 to 3.6 4.6 7.6 3.0 to 5.5 8.0 12.7 2.7 to 3.6 4.0 7.3 2.7 to 5.5 6.6 11.3 min Specification typ max unit
Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified
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No.A1384-21/30
LC87F2J32A
Continued from preceding page.
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(11) Symbol IDDOP(10) Pin/ Remarks VDD1 Conditions VDD[V] * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * Ta=-10 to +50C HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(1) VDD1 * HALT mode * FmCF=12MHz ceramic oscillation mode * System clock set to 12MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(2) * HALT mode * CF1=24MHz external clock * System clock set to CF1 side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDHALT(3) * HALT mode * FmCF=10MHz ceramic oscillation mode * System clock set to 10MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(4) * HALT mode * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(5) * HALT mode * CF oscillation low amplifier size selected. (CFLAMP=1) * FmCF=4MHz ceramic oscillation mode * System clock set to 4 MHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/4 frequency division ratio IDDHALT(6) * HALT mode * FsX'tal=32.768 kHz crystal oscillation mode * Internal Low speed RC oscillation stopped. * System clock set to internal Medium speed RC oscillation * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio 1.8 to 3.6 0.2 0.5 1.8 to 5.5 0.3 0.9 2.2 to 3.6 0.3 0.7 2.2 to 5.5 0.6 1.5 1.8 to 3.6 0.6 1.4 1.8 to 5.5 1.2 3.0 mA 2.2 to 3.6 1.2 2.3 2.2 to 5.5 2.2 4.4 3.0 to 3.6 2.0 3.4 3.0 to 5.5 4.0 6.9 2.7 to 3.6 1.4 2.5 2.7 to 5.5 2.6 4.7 2.5 8.1 22 3.3 13 33 5.0 27 84 A 1.8 to 3.6 13 59 1.8 to 5.5 27 120 min Specification typ max unit
Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified
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No.A1384-22/30
LC87F2J32A
Continued from preceding page
Parameter HALT mode consumption current (Note 9-1) (Note 9-2) Symbol IDDHALT(7) Pin/ remarks VDD1 * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * Internal Low speed and Medium speed RC oscillation stopped. * System clock set to 8MHz with Frequency variable RC oscillation * 1/1 frequency division ratio IDDHALT(8) * HALT mode * External FsX'tal and FmCF oscillation stopped. * System clock set to internal Low speed RC oscillation. * Internal Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(9) * HALT mode * External FsX'tal and FmCF oscillation stopped. * System clock set to internal Low speed RC oscillation. * Internal Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * Ta=-10 to +50C IDDHALT(10) * HALT mode * FsX'tal=32.768 kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDHALT(11) * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal Low speed and Medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * Ta=-10 to +50C HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(2) IDDHOLD(1) VDD1 HOLD mode * CF1=VDD or open (External clock mode) HOLD mode * CF1=VDD or open (External clock mode) * Ta=-10 to +50C IDDHOLD(3) HOLD mode * CF1=VDD or open (External clock mode) * LVD option selected IDDHOLD(4) HOLD mode * CF1=VDD or open (External clock mode) * Ta=-10 to +50C * LVD option selected Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) IDDHOLD(5) VDD1 Timer HOLD mode * FsX'tal=32.768kHz crystal oscillation mode Timer HOLD mode * FsX'tal=32.768kHz crystal oscillation mode * Ta=-10 to +50C 2.5 1.8 to 5.5 1.8 to 3.6 5.0 3.3 2.5 1.9 14 4.8 14 4.8 2.4 3.4 89 38 40 15 7.6 3.3 2.2 4.1 3.3 2.5 1.8 to 5.5 1.8 to 3.6 5.0 0.02 0.015 2.9 2.2 2.9 1.2 0.9 35 18 A 7.2 1.8 to 3.6 5.0 0.02 0.04 14 2.8 1.8 to 5.5 0.04 30 2.5 3.4 11 3.3 6.2 18 5.0 16 56 1.8 to 3.6 6.2 43 1.8 to 5.5 16 96 2.5 10 18 3.3 15 26 A 5.0 26 52 1.8 to 3.6 15 48 1.8 to 5.5 26 91 2.7 to 3.6 1.4 2.6 2.7 to 5.5 2.5 5.0 Conditions VDD[V] min. Specification typ. max. unit
Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified
No.A1384-23/30
LC87F2J32A
F-ROM Programming Characteristics at Ta = -10C to +55C, VSS1 = VSS2 = VSS3 = 0V
Parameter Onboard programming current Programming time tFW(1) tFW(2) * Erasing time * Programming time 2.2 to 5.5 20 40 30 60 ms s Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] * Only current of the Flash block. 2.2 to 5.5 5 10 mA min Specification typ max unit
UART (Full Duplex) Operating Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P20), URX(P21) Conditions VDD[V] 1.8 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC
Data length: Stop bits: Parity bits:
7, 8, and 9 bits (LSB first) 1 bit (2-bit in continuous data transmission) None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Start bit Start of reception Receive data (LSB first) Stop bit End of reception
UBR
No.A1384-24/30
LC87F2J32A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator * CF oscillation normal amplifier size selected (CFLAMP=0)
Nominal Frequency 12MHz 10MHz Vendor Name Circuit Constant Oscillator Name C1 [pF] CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 8MHz MURATA 6MHz CSTCE8M00G52-R0 CSTLS8M00G53-B0 CSTCR6M00G53-R0 CSTLS6M00G53-B0 4MHz CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (10) (15) (15) (15) (15) (15) C2 [pF] (10) (10) (15) (10) (15) (15) (15) (15) (15) Rf1 [] Open Open Open Open Open Open Open Open Open Rd1 [] 680 680 680 1.0k 1.0k 1.5k 1.5k 1.5k 1.5k Operating Voltage Range [V] 2.7 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 1.8 to 5.5 1.8 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 max [ms] 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.6 0.6 Internal C1,C2 Remarks
* CF oscillation low amplifier size selected (CFLAMP=1)
Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 4MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 (15) (15) C2 [pF] (15) (15) Rf1 [] Open Open Rd1 [] 1.0k 1.0k Operating Voltage Range [V] 1.9 to 5.5 1.9 to 5.5 Oscillation Stabilization Time typ [ms] 0.2 0.2 max [ms] 0.6 0.6 Internal C1,C2 Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4).
No.A1384-25/30
LC87F2J32A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency Circuit Constant Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 C4 [pF] 18 Rf2 [] Open Rd2 [] 330k Operating Voltage Range [V] 1.8 to.5.5 Oscillation Stabilization Time typ [s] 1.4 max [s] Applicable 4.0 CL value= 7.0pF Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf1 Rd1
Rf2 Rd2
C1 CF
C2
C3 X'tal
C4
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1384-26/30
LC87F2J32A
VDD Power supply Operating VDD lower limit 0V Reset time RES
Internal Medium speed RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal valid
Internal Medium speed RC oscillation or Low speed RC oscillation CF1, CF2
tmsCF
tmsX'tal XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 4 Oscillation Stabilization Times
No.A1384-27/30
LC87F2J32A
VDD
RRES
RES CRES
Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user's manual for more information.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (SIO0 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1384-28/30
LC87F2J32A
POR release voltage(PORRL)
(a)
(b)
VDD
Reset period Unknown-state (POUKS) RES
100s or longer
Reset period
Figure 8 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) * The POR function generates a reset only when power is turned on starting at the VSS level. * No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. * A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer.
LVD hysteresis width (LVHYS)
LVD release voltage (LVDET+LVHYS)
VDD Reset period Unknown-state (LVUKS) RES Reset period Reset period LVD reset voltage (LVDET)
Figure 9 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) * Resets are generated both when power is turned on and when the power level lowers. * A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level.
No.A1384-29/30
LC87F2J32A
VDD
LVD release voltage LVD reset voltage tLVDW VSS
LVDET-0.5V
Figure 10 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform)
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of April, 2009. Specifications and information herein are subject to change without notice.
PS No.A1384-30/30

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